There has hitherto been a method by which a processor of an information processing apparatus performs a test by executing a test program as a memory testing method in the information processing apparatus including a memory as instanced by LSI (Large Scale Integration) and other equivalent semiconductor integrated circuits. There is also a method of performing the test, in which, e.g., a controller to start the test sets a command in an instruction queue within the processor. In the case of the instruction queue, the processor on the information processing apparatus accesses the memory via the instruction queue, thereby executing the test. FIG. 1 illustrates a configuration of the information processing apparatus including the memory.
The information processing apparatus in FIG. 1 includes a processor 301, a memory 303 and a controller 304. The processor 301 includes a core 310, and a memory control device 320 that accesses the memory 3. The core 310 includes an instruction queue 311 having a plurality of entries. In FIG. 1, each entry is depicted by a character string “queue”. The controller 304 outside the processor 301 can set and read the data in and from the instruction queue 311. The controller 304 sets a command for testing the memory 303 in the instruction queue 311, and starts the test.
The memory control device 320 includes a request queue 321 having a plurality of entries, an access control unit 322 and a reception data control unit 323. The memory control device 320 acquires the command or the data for accessing the memory from a control circuit to control the instruction queue 311 within the core 310, and hands over the command or the data to the access control unit 322. The access control unit 322 acquires the command or the data via the request queue 321, and access the memory 303. The access control unit 322 is in the midst of executing some sort of process, during which the access control unit 322 returns a busy signal A1 to the control circuit of the request queue 321.
During a period for which the busy signal A1 is set ON, the control circuit of the request queue 321 stops handing over the next command or data to the access control unit 322. When the data are handed over to, e.g., the reception data control unit 323 from the memory 303, the access control unit 322 sets OFF the busy signal A1, based on a response signal A2 transmitted from the reception data control unit 323. When the busy signal A1 is set OFF, the control circuit of the request queue 321 hands over the request containing the next command or data to the access control unit 322 and the access control unit 322 executes a next process for the memory 303 upon receiving the next request. As described above, the memory 303 included in the information processing apparatus has hitherto been tested by setting the command or the data in the instruction queue 311 within the processor 310 from the controller 304.
For instance, tests called a load test (termed also a running test), a disturb test and other equivalent tests are performed as the tests of the information processing apparatus including the memory described above. However, the information processing apparatus of recent years involves a complicated behavior of the processor due to mounting a plurality of cores, diversifying a cache, diversifying a function of an interconnect between plural processors, and other equivalent schemes. It is assumed that the disturb test, the load test and other equivalent tests are not easily implemented under control of a program to be executed by the processor or under control of the instruction queue provided within the processor due to the complicated behavior of the processor.    [Patent document 1] International Publication Pamphlet No. WO 2002/073411    [Patent document 2] Japanese Laid-Open Patent Publication No. 2013-30909